(1) Field of the Invention
The invention relates to the method of fabrication of integrated circuit devices, and more particularly, to a method of forming a sub-quarter-micron MOSFET structure in the fabrication of integrated circuits.
(2) Description of the Prior Art
In sub-quarter-micron MOSFET architecture, it is necessary to use ultra-shallow source and drain extension regions. Low energy ion implantation is typically used to form such regions.
For example, FIG. 1 illustrates a semiconductor substrate 10, preferably composed of monocrystalline silicon. A layer of silicon oxide 12 is formed on the surface of the substrate. A polysilicon layer is deposited and patterned to form gate electrode 16. A typical LDD (lightly doped source and drain) structure 24 is formed by an LDD mask implant followed by deposition of the spacer oxide 18 and then a source/drain mask implant 20. Lightly doped source and drain regions 24 lie under the spacers 18 as shown in FIG. 1.
Gate critical dimension (CD) reproducibility has been a concern of all of the sub-micron technologies. Minimum gate length corresponds to the minimum feature size of any technology generation; that is, the edges of the lithography tool capability. Therefore, considerable relative variations of a gate CD are inevitable. At the same time, device characteristics strongly depend on the gate length.
U.S. Pat. No. 5,447,874 to Grivna et al teaches a method of forming a MOSFET device employing a dual metal gate formed in an oxide opening. Using a chemical mechanical polishing step to planarize the surface eliminates the problems encountered in etching different metals. U.S. Pat. No. 5,856,225 to Lee et al teaches a method of forming a MOSFET device where the source/drain regions are built prior to the implantation of the channel region under the gate. This allows more precise control of the source/drain positions, thereby controlling the electrical parameters of the MOSFET device. U.S. Pat. No. 5,393,681 to Witek et al teaches a method of forming a vertically raised transistor using selective epitaxial growth (SEG) to form the channel region of a MOSFET. U.S. Pat. No. 5,391,506 to Tada et al teaches a method for forming a transistor in a projection formed in the substrate. U.S. Pat. No. 5,624,863 to Helm et al teaches a method where the source and drain of a MOSFET are formed using out-diffusion from a doped silicon plug into the substrate.